This invention relates to methods and apparatus for treating a semiconductor substrate, such as a semi-conductor wafer, and, in particular, but not exclusively, to methods and apparatus for providing a low dielectric constant (known as low k) layer in a planarisation or gap filling operation.
In our earlier co-pending patent application WO94/01885, the contents of which are incorporated herein by reference, we describe a planarisation technique in which a liquid short-chain polymer is formed on a semiconductor wafer by reacting silane (SiH.sub.4) with hydrogen peroxide (H.sub.2 O.sub.2). The polymer, which initially is in a liquid state, is formed on to a wafer to produce planarisation either locally or globally, or gap filling. This technique provides a planarisation or gap filling layer of silicon dioxide and we have found it to be a most suitable material for semiconductor circuit manufacturing.